1. Field of the Invention
The present invention relates to a semiconductor device, a routing method and manufacturing method of a semiconductor device. More particularly, the present invention relates to a semiconductor device in which interconnections can be routed properly, a routing method and manufacturing method of a semiconductor device which can route interconnections of the semiconductor device properly.
2. Description of the Related Art
In the layout design of a large scale integrated circuit (LSI), a placement and routing system is known, which automatically places logic cells and logic blocks (hereinafter referred to as logic cells/blocks) and routes interconnections (for example, Japanese Patent 3390393). The placement and routing system is exemplified in a CAD (Computer Aided Design) system. The placement and routing operation for using the placement and routing system is carried out, for example, as follows. At first, it reads the data with regard to the circuit diagram of a LSI of a design target, the data of logic cells/blocks prepared in a library, and the data with regard to a design rule. Next, it places the logic cells/blocks, based on the respective read data. Then, it routes interconnections among the placed logic cells/blocks based on the respective read data. After that, it verifies whether or not there is any trouble in the placement and routing, and carries out the re-placement and the re-routing if necessary. Finally, it generates the artwork data with regard to the routing of the entire chip corresponding to patterns in respective layers constituting the LSI based on the data of the placement and routing system.
Those, which are automatically placed and routed, are exemplified in followings. Those are: a thin interconnection, a thick interconnection and a macro (logic cells/blocks). The thin interconnection is thin in line width and exemplified in a signal interconnection. The thick interconnection is thicker in line width than the thin interconnection and exemplified in a power supply interconnection and a ground interconnection. The macro (logic cells/blocks) is exemplified in a memory. Here, a case of connecting the thin interconnection and a thick width figure is explained as an example. The thick width figure has a thick width as compared with the thin interconnection such as the macro and the thick interconnection.
FIG. 1 is an example of a layout view showing the connection between the thin interconnection and the thick width figure in the conventional placement and routing. Along grid lines 121 in an X-direction and grid lines 122 in a Y-direction, an interconnection A 111 and an interconnection B112 are respectively routed. One end of the interconnection A 111 (interconnections A 111-1 to 111-3) is connected to one end of s thick width FIG. 115. Around the thick width FIG. 115, a thick width spacing area 117 is provided based on the design rule.
The interconnection A 111 is routed in the vicinity of the portion connected to the thick width FIG. 115, based on the predetermined design rule. The design rule is the minimum spacing rule. The rule is that a interconnection (111) is bent at the position away from the thick width FIG. (115) by a minimum spacing (119) or more, when the interconnection (111) connected to the thick width FIG. (115) is bent in the same layer as the thick width FIG. (115). This minimum spacing rule, for example, enables the protection against the influence of microloading effect.
Here, the microloading effect implies the phenomenon of the etching trouble in the photolithography. The phenomenon is caused by a fact that an etching manner is different depending on a position, when a pattern having a high density and a pattern having a low density are etched at the same time. In the example of FIG. 1, such effect easily occurs in the connection portion between the thick width FIG. 115 and the interconnection A 111. For this reason, the minimum spacing rule is applied.
In the case of FIG. 1 in the routing, after the interconnection A 111 is routed as close as possible to the thick width FIG. 115, both are connected to each other. For this reason, the bent point is inevitably located at the distance of the minimum spacing 119. Then, the interconnections A 111-1 to A 111-2 connected to the thick width FIG. 115 are placed within a predetermined distance Y defined from the connection portion (the predetermined distance Y>the minimum spacing 119). In such a case, under the design rule, the minimum spacing rule of the thick width FIG. 115 is applied to the interconnections A 111-1 to A 111-2. That is, the thick width spacing area 117 for the thick width FIG. 115 is also enlarged around the interconnections A 111-1 to A 111-2.
A interconnection B 112 can not enter the thick width spacing area 117 because of the design rule. For this reason, the interconnection B 112 is routed along grid lines Tx5-Ty1-Tx6-Ty6-Tx5. That is, the interconnection B 112 is routed so as to make a detour around the thick width spacing area 117, in the vicinity of the connection portion to the thick width FIG. 115. Thus, the interconnection B 112 is routed so as to make the detour around the interconnection A 111-2, although there is no problem on the design even if it is routed only on the grid line Tx5. Consequently, not only the routing resource (routing region) is reduced, but also the interconnection length becomes long.
Thus, in the connection portion between the thick width FIG. 115 and the interconnection A 111, there may be a possibility that the thick width spacing area 117 is wider than necessary. A technique is required for suitably setting a region to regulate the routing in the connection portion between the thick width figure and the thin interconnection. A technique is desired for suitably setting the interconnection laid in the vicinity of the connection region between the thick width figure and the thin interconnection. And, a technique is desired for suitably setting the routing region in the vicinity of the connection region between the thick width figure and the thin interconnection and protecting the interconnection length from being longer than necessary.
In the above-mentioned Japanese Patent No. 3390393, a routing method of a placement and routing system is disclosed. The routing method of a placement and routing system routs interconnections on grids with a predetermined pitch. Via cells are registered in a library and includes a rectangular via, a lower interconnection layer and an upper interconnection layer covering the rectangular via. The routing method includes the steps of: detecting that a spacing between interconnection is less than the minimum spacing with no limitation of facing interconnection length, and equal to or more than the short run spacing allowing a certain spacing with a certain limitation of facing interconnection length when the via cells are placed on adjacent grids facing each other; generating the via cell data modifying the via margin such that the spacing can satisfy the minimum spacing with no limitation of facing interconnection length when via cells are placed in facing each other; and replacing the via cell data to the artwork data corresponding to the via cell after placing and routing by the placement and routing system based on the via cell data.